PE Computer Engineering Study Guide: 8 Topics & 16-Week Plan

The PE Electrical and Computer: Computer Engineering exam is broad in a very specific way: bit-level representation, architecture, systems software, applications, digital devices, networks, cybersecurity, and quality all sit on the same test. Under the current NCEES spec (effective October 2025), the exam is a single 85-question linear session across 8 official topic areas. This guide gives you the topic map, the high-return study order, and a 16-week plan built for working engineers.

What Is the Exam Format?

The PE Computer Engineering exam is computer-based, administered on a single annual test date at Pearson VUE centers, and costs $400. The appointment covers 8 hours of exam time plus a 30-minute scheduled break. Under the October 2025 spec, the exam is a single continuous 85-question session — there is no longer a morning/afternoon split or separate breadth/depth structure. The exam is closed-book, so practice should focus on recognizing the problem family, using the reference handbook efficiently, and avoiding small representation or logic mistakes.

PE Topic Resource Map

Where to Review the Highest-Return PE Computer Engineering Topics

Use this map to keep the PE Computer Engineering exam from turning into eight unrelated review piles. The best route is representation, architecture, systems, software, digital logic, networks, security, and quality as connected engineering workflows.

Highest return Computer Architecture and Data Representation

Connect bits, memory, datapaths and performance.

Number systems, floating point, caches, pipelines, instruction sets, memory hierarchy, interrupts, and performance metrics should be reviewed together because the exam often crosses those boundaries.

• Reference lane: Data Representation and Computer Architecture.
• Practice move: write bit width, address size, cache organization, and timing assumptions before solving.

Reference/code guide Practice this discipline Open MIT Computation Structures

High return Systems Software

Follow the boundary between hardware, OS and compiler behavior.

Operating systems, processes, threads, memory management, file systems, interrupts, scheduling, linking, and compilation require clean system-boundary thinking.

• Reference lane: Systems Software and Computer Architecture.
• Practice move: identify whether the behavior belongs to hardware, kernel, runtime, compiler, or application code.

Reference/code guide Practice this discipline Open MIT Operating Systems

High return Digital Devices and Digital Electronics

Reduce logic problems to truth tables, timing or state.

Boolean logic, gates, flip-flops, FSMs, timing, setup/hold, CMOS behavior, ADC/DAC ideas, and basic electronics reward structured representation.

• Reference lane: Digital Devices and Digital Electronics.
• Practice move: draw the truth table, timing diagram, or state transition before simplifying.

Reference/code guide Practice this discipline Open MIT Digital Systems

High return Networks and Cybersecurity

Separate protocol behavior from security controls.

Networks, routing, addressing, transport behavior, cryptography, authentication, authorization, vulnerabilities, and risk controls are easiest when architecture and threat model are clear.

• Reference lane: Computer Networks and Cybersecurity.
• Practice move: identify layer, asset, threat, control, and failure mode before answering.

Reference/code guide Practice this discipline Open NIST CSRC

Steady points Application Development and Quality Processes

Turn software questions into lifecycle and test decisions.

Requirements, design, data structures, algorithms, testing, configuration management, reliability, quality processes, and secure development are high-value review lanes for working engineers.

• Reference lane: Application Development and Quality Processes.
• Practice move: decide whether the question asks about implementation, testing, process, security, or maintainability.

Reference/code guide Practice this discipline Open OWASP ASVS

Source note: topic names, reference documents, design standards, and editions should be checked against the current NCEES PE exam page and your exam specification. PE guidance here is section/code-lane based only and intentionally does not promise page numbers for external standards.

The 8 NCEES Topic Areas

The current blueprint groups everything you need to know into 8 topic areas. Priorities below reflect the NCEES question ranges (a higher range means more questions, which means more study time).

1. Data Representation (7–11 questions) — Priority: HIGH

Data representation covers how computers store and manipulate numbers, text, and symbolic data at the bit level. Problems tend to be short and calculation-heavy: given a representation, convert it; given a number, find its representation.

Key subtopics: Number systems (binary, octal, hexadecimal, conversion between bases), signed-integer formats (sign-magnitude, one’s complement, two’s complement), floating-point representation (IEEE 754 single and double precision, rounding modes, NaN and infinity), character encodings (ASCII, Unicode, UTF-8), endianness (big vs. little), and error-detection/correction codes (parity, checksums, Hamming codes, CRC).

Critical formulas and facts:

• Two’s complement: negate by inverting all bits and adding 1; range for n bits is −2ⁿ⁻¹ to 2ⁿ⁻¹−1
• IEEE 754 single: 1 sign bit + 8 exponent bits (bias 127) + 23 fraction bits
• IEEE 754 double: 1 sign bit + 11 exponent bits (bias 1023) + 52 fraction bits
• Hamming distance: minimum bit flips to transform one code word into another; d must be ≥ 2t+1 to correct t-bit errors
• Maximum n-bit unsigned integer = 2ⁿ−1

Tips: Master base conversions cold — especially hex ↔ binary (every hex digit = 4 bits). Two’s complement arithmetic questions are routine; practice negation and subtraction until they feel automatic. For IEEE 754 questions, memorize the bit layout so you can decode a given 32-bit hex string without hesitation.

2. Computer Architecture (12–18 questions) — Priority: HIGHEST

Computer Architecture is the largest single topic on the exam — up to one in five questions. Expect questions on instruction-level organization, memory hierarchy, pipelining, and performance analysis. Problems are often multi-step: compute an address, determine a cache hit, then calculate effective access time.

Key subtopics: Instruction set architecture (RISC vs. CISC, addressing modes, instruction formats), pipelining (5-stage MIPS pipeline, structural/data/control hazards, forwarding, stalls), cache memory (direct-mapped, set-associative, fully associative, replacement policies, write-through vs. write-back), virtual memory (paging, page tables, TLB, segmentation), memory hierarchy (registers, L1/L2/L3 cache, main memory, secondary storage), bus architecture, and performance metrics.

Critical formulas:

• CPU time = instruction count × CPI × clock period = IC × CPI / clock rate
• Amdahl’s law: speedup = 1 / ((1−p) + p/s), where p is the parallelizable fraction and s is the speedup of that fraction
• Effective access time (2-level cache): T_eff = h × T_hit + (1−h) × T_miss
• Direct-mapped cache: block address mod number of blocks = cache index
• Page table size = number of pages × page table entry size; number of pages = virtual address space / page size

Tips: Practice cache address decomposition until it is second nature — given an address and a cache configuration, split into tag, index, and offset bits, then determine hit/miss. Pipeline hazard questions show diagrams; trace them cycle-by-cycle. Amdahl’s law questions are frequent and highly predictable.

3. Systems Software (9–14 questions) — Priority: HIGH

Systems Software covers operating systems, compilers, interpreters, and the software layer between applications and hardware. Questions focus on concepts and trade-offs rather than code.

Key subtopics: Operating-system fundamentals (processes vs. threads, context switching, scheduling algorithms including FCFS/SJF/Round-Robin/priority/multilevel feedback), synchronization (mutexes, semaphores, monitors, deadlock conditions and prevention), memory management (paging, swapping, fragmentation, garbage collection), file systems (inode structure, block allocation, journaling), compilers vs. interpreters (lexical analysis, parsing, semantic analysis, code generation, optimization), and linking and loading (static vs. dynamic, symbol resolution).

Key facts and rules:

• Four Coffman conditions for deadlock: mutual exclusion, hold-and-wait, no preemption, circular wait — breaking any one prevents deadlock
• Average waiting time (FCFS) = mean of start-time−arrival-time across all processes
• Banker’s algorithm: safe state iff there exists an execution order where every process can finish
• Compiler phases: lexer → parser → semantic analyzer → intermediate code generator → optimizer → code generator
• Virtual memory thrashing: page fault rate so high that CPU utilization collapses

Tips: Scheduling problems are standard — practice computing average waiting and turnaround times for each algorithm on a given process set. Deadlock questions frequently test the four Coffman conditions. For compilers, focus on recognizing what each phase produces rather than writing grammars.

4. Application Development (8–12 questions) — Priority: HIGH

Application Development covers the engineering discipline of writing correct, maintainable software: programming languages, data structures, algorithms, testing, and software engineering process.

Key subtopics: Data structures (arrays, linked lists, stacks, queues, trees, heaps, hash tables, graphs) and their Big-O time/space complexity, algorithms (sorting, searching, traversal, dynamic programming basics), object-oriented concepts (encapsulation, inheritance, polymorphism, composition), software development life cycle models (waterfall, agile, spiral, V-model), testing methodologies (unit, integration, system, regression, black-box vs. white-box, code coverage), design patterns (singleton, factory, observer, MVC), and version control concepts.

Big-O you should know cold:

• Array indexing: O(1); search unsorted: O(n); search sorted (binary search): O(log n)
• Linked list: indexing O(n), insertion at known position O(1)
• Binary search tree: average O(log n), worst case O(n) (unbalanced); balanced BST: O(log n) guaranteed
• Hash table: average O(1) lookup/insert; worst case O(n) with pathological collisions
• Sorting: bubble/insertion/selection O(n²); merge/heap/quick O(n log n) average; radix/counting O(n) under constraints

Tips: Big-O questions are the most predictable on this topic. Practice identifying the dominant term in a pseudocode fragment. SDLC questions reward specific recognition of each model’s strengths and weaknesses — know why agile handles changing requirements better than waterfall, etc. Testing questions often ask what type of test a scenario describes.

5. Digital Devices (8–12 questions) — Priority: HIGH

Digital Devices covers the physical implementation of digital logic — transistors, logic families, and the device-level characteristics that constrain practical circuits.

Key subtopics: CMOS transistor operation (NMOS and PMOS, pull-up/pull-down networks, threshold voltage, propagation delay), logic families (TTL, CMOS, ECL, LVDS) and their voltage levels and noise margins, fan-in and fan-out, driving capacitive loads, power consumption (static, dynamic, P = CV²f), clock distribution and skew, memory devices (SRAM vs. DRAM, refresh, ROM variants), and programmable devices (PLAs, PALs, FPGAs, ASICs).

Critical formulas:

• CMOS dynamic power: P_dyn = α · C_L · V_DD² · f (where α is activity factor)
• Propagation delay: t_pd scales with C_L and inversely with drive strength
• Noise margin high: NM_H = V_OH(min) − V_IH(min)
• Noise margin low: NM_L = V_IL(max) − V_OL(max)
• DRAM refresh interval: total refresh time ÷ number of rows

Tips: Know the power-delay trade-off in CMOS. Questions often ask which logic family is appropriate for a given voltage, speed, or power constraint. For memory, SRAM vs. DRAM trade-offs (speed, density, refresh, cost) are routinely tested.

6. Digital Electronics (8–12 questions) — Priority: HIGH

Digital Electronics covers logic design above the transistor level: Boolean algebra, combinational and sequential circuits, and state-machine design. This topic is routine and formula-driven once you know the basics.

Key subtopics: Boolean algebra (laws, De Morgan’s, simplification), Karnaugh maps (2-, 3-, 4-variable, don’t-care conditions, POS and SOP forms), combinational logic (decoders, encoders, multiplexers, demultiplexers, adders, comparators), sequential logic (latches, flip-flops — SR, D, JK, T), finite state machines (Mealy vs. Moore, state diagrams, state tables, state minimization), timing analysis (setup/hold times, metastability, clock-to-Q delay), and hardware description languages (VHDL/Verilog structural vs. behavioral styles).

Key rules:

• De Morgan’s: (AB)’ = A’ + B’; (A+B)’ = A’B’
• K-map simplification: group adjacent 1s in powers of 2 (1, 2, 4, 8...); larger groups produce smaller product terms
• Number of states for n flip-flops: 2ⁿ
• Maximum clock frequency: f_max = 1 / (t_clk-to-Q + t_{combinational} + t_setup)
• Full adder: sum = A ⊕ B ⊕ C_in; carry = AB + C_in(A ⊕ B)

Tips: State-machine design is heavily tested. Practice the full workflow end-to-end: given a specification, draw the state diagram, derive the state table, pick a state encoding, write the flip-flop input equations, and draw the circuit. K-map simplification problems are standard — be fluent up to 4 variables.

7. Computer Networks and Cybersecurity (11–17 questions) — Priority: HIGHEST

Computer Networks and Cybersecurity is the second-largest topic on the exam (tied with Computer Architecture for highest weight). It spans the OSI/TCP-IP stack, common protocols, and core security concepts. Subnetting alone can account for several questions.

Networking subtopics: OSI 7-layer model and TCP/IP 4-layer model (mapping between them), physical layer and cabling basics, data-link layer (Ethernet, MAC addressing, switches, VLANs, ARP), network layer (IP addressing, subnetting, CIDR, routing protocols — RIP, OSPF, BGP, ICMP), transport layer (TCP vs. UDP, ports, flow control, congestion control, three-way handshake), application layer (DNS, HTTP/HTTPS, SMTP, FTP), and wireless basics (802.11 families).

Cybersecurity subtopics: Symmetric encryption (AES, DES, 3DES, block modes — ECB, CBC, CTR), asymmetric encryption (RSA, elliptic curve, key exchange), cryptographic hash functions (SHA family, MD5 and why it is broken, collisions), digital signatures and certificates (PKI, X.509, CA hierarchy), authentication protocols (Kerberos, OAuth basics), common attacks (MITM, replay, buffer overflow, SQL injection, XSS, DDoS) and defenses, and network-security devices (firewalls, IDS/IPS, VPNs).

Must-know subnetting rules:

• Given CIDR /n, number of host bits = 32 − n, number of usable hosts = 2⁽³²⁻ⁿ⁾ − 2
• Subnet mask: /n means n leading 1s followed by (32−n) 0s — convert to dotted decimal
• Network address = IP AND mask; broadcast address = network OR inverted mask
• Private ranges: 10.0.0.0/8, 172.16.0.0/12, 192.168.0.0/16
• TCP three-way handshake: SYN → SYN-ACK → ACK; connection teardown uses FIN/ACK pairs

Tips: Practice subnetting until you can determine network, broadcast, usable host range, and host count in under 60 seconds without a calculator. Know which layer each protocol operates at. For cryptography, know the difference between confidentiality (encryption) and integrity (hashing) and which algorithms provide each.

8. Quality Processes (7–11 questions) — Priority: MEDIUM

Quality Processes covers the engineering discipline of managing quality in computer systems: requirements, reliability, testing, and process improvement. Questions are concept-driven rather than computational.

Key subtopics: Requirements engineering (functional vs. non-functional requirements, traceability, verification vs. validation), reliability metrics (MTBF, MTTR, availability), fault tolerance (redundancy types: active/standby, N-version programming, hot vs. cold standby), risk management (identification, mitigation, contingency planning), configuration management and change control, quality-assurance frameworks (ISO 9001, CMMI, ITIL concepts), software metrics (cyclomatic complexity, defect density), and professional/ethical responsibilities (IEEE and NSPE codes of ethics, public safety primacy).

Key formulas:

• MTBF (mean time between failures) = total operating time ÷ number of failures
• Availability = MTBF / (MTBF + MTTR)
• Reliability of parallel (redundant) system of n identical components: 1 − (1−R)ⁿ
• Reliability of series system: R_total = ∏ R_i
• Cyclomatic complexity = edges − nodes + 2 (in a control-flow graph)

Tips: Reliability math is the most computable part of this topic — know series vs. parallel reliability formulas and when each applies. For ethics, the public-safety-paramount principle is the single most common correct answer. Verification-vs-validation questions hinge on the distinction: verification = “did we build the thing right?”; validation = “did we build the right thing?”

Topic Priority Table

Topic	Est. Questions	% of Exam	Priority
Computer Architecture	12–18	~18%	HIGHEST
Computer Networks and Cybersecurity	11–17	~16%	HIGHEST
Systems Software	9–14	~13%	HIGH
Application Development	8–12	~12%	HIGH
Digital Devices	8–12	~12%	HIGH
Digital Electronics	8–12	~12%	HIGH
Data Representation	7–11	~11%	HIGH
Quality Processes	7–11	~11%	MEDIUM

Every topic on the current blueprint is worth at least 7 questions — there are no “low-weight” topics to safely skip. The two HIGHEST-priority topics (Computer Architecture and Computer Networks + Cybersecurity) together can account for more than a third of the exam, so invest study time there first.

How Should You Structure a 16-Week Study Plan?

Most PE Computer Engineering candidates study 200–400 hours over 12 to 20 weeks while working full-time. The plan below assumes roughly 15–25 hours per week and sequences topics from foundational (Data Representation, Digital Devices) to applied (Networks, Quality). Adjust the pace to your schedule, but do not skip the practice-exam milestones.

• Week 1: Take a diagnostic practice exam under timed conditions. Score it honestly, identify your weakest three topic areas, and organize study materials. Download and review the NCEES PE Computer Engineering Reference Handbook — learn its structure and where key formulas live.
• Week 2: Data Representation. Master base conversions, two’s complement arithmetic, IEEE 754 single/double precision, and error-detection codes. Work 30+ practice problems — this topic rewards mechanical fluency.
• Weeks 3–4: Digital Electronics and Digital Devices. Boolean algebra, K-maps, combinational and sequential logic, state-machine design end-to-end, CMOS power and delay, memory device trade-offs. These two topics share fundamentals and are best studied together. Work at least 40 problems.
• Weeks 5–7: Computer Architecture. The largest topic. Instruction sets, pipelining with hazard analysis, cache address decomposition, virtual memory, Amdahl’s law. Plan 50+ practice problems. Expect cache and pipeline diagram questions on every practice exam.
• Week 8: Mid-plan checkpoint — take a 40-question mixed topic practice exam. Score it and identify which topics still need work before moving on.
• Week 9: Systems Software. Process vs. thread, scheduling algorithms, synchronization and deadlock (Coffman conditions), memory management, compiler phases. Work scheduling problems for every algorithm.
• Week 10: Application Development. Big-O for every data structure and major algorithm, SDLC models, testing methodologies, design patterns. Practice recognizing the dominant Big-O term in pseudocode.
• Weeks 11–12: Computer Networks and Cybersecurity. OSI/TCP-IP, subnetting drills (aim to subnet in under 60 seconds), TCP three-way handshake, DNS/HTTP basics, symmetric vs. asymmetric crypto, hash functions, common attacks. Subnet practice every day.
• Week 13: Quality Processes. Reliability math (series/parallel), MTBF/MTTR/availability, verification vs. validation, ethics (public safety paramount). Lightest topic — do not over-invest.
• Week 14: Catch-Up and Weak Areas. Revisit topics where diagnostic and mid-plan scores were lowest. Work mixed-topic problem sets that force you to identify which topic each question belongs to — this simulates the exam experience.
• Week 15: Full-length 85-question timed practice exam under realistic conditions. Use only the NCEES reference handbook, take one 30-minute break, enforce the 8-hour time limit. Score by topic area.
• Week 16: Final review. Review every practice exam question you missed. Drill your weakest formulas. Ensure you can subnet, build a K-map, derive cache parameters, and apply Amdahl’s law without hesitation. Rest the day before the exam.

What Reference Materials Do You Need?

The exam is closed-book — only the NCEES-provided digital reference handbook is available during testing. Your study preparation should draw from these authoritative sources:

• NCEES PE Electrical and Computer Reference Handbook — Your only exam reference. Study with this as your sole technical resource during practice exams. Learn where every formula, table, and chart is located so you can find them within seconds on exam day.
• Patterson & Hennessy, “Computer Organization and Design” — The standard reference for pipelining, cache design, virtual memory, and performance analysis. Covers Amdahl’s law and CPI calculations thoroughly.
• Mano & Ciletti, “Digital Design” — Comprehensive coverage of combinational and sequential logic, state machines, and HDL. The definitive reference for the Digital Electronics topic.
• Tanenbaum & Bos, “Modern Operating Systems” — Standard reference for scheduling, synchronization, deadlock, and memory management. Covers the Systems Software topic end to end.
• Kurose & Ross, “Computer Networking: A Top-Down Approach” — Clear explanations of TCP/IP, routing, transport layer, and network security. Good for both the Networks and Cybersecurity portions of the single combined topic.
• Cormen et al., “Introduction to Algorithms” — Canonical reference for data structures, Big-O, and algorithm analysis. More depth than the exam requires, but the first few chapters are gold.

What Study Tips Are Specific to Computer Engineering?

• Subnetting is the single highest-ROI skill. Networks and Cybersecurity questions commonly include subnetting. Given CIDR notation, you should produce the network address, broadcast address, usable host range, and host count in under 60 seconds. Drill it every day for at least two weeks.
• Practice cache address decomposition end-to-end. Computer Architecture is the largest topic and cache questions are among the most predictable. Given an address and a cache configuration, split into tag/index/offset bits, determine hit/miss, and compute effective access time.
• Know your state machines cold. Digital Electronics problems commonly ask for state-diagram-to-circuit conversion. Practice Mealy and Moore machines through the full workflow: diagram → table → flip-flop input equations → circuit.
• Do not memorize HDL syntax. The exam may include VHDL or Verilog snippets, but it tests your ability to read and interpret hardware descriptions, not write production code. Trace the logic described by each fragment.
• Big-O fluency beats algorithm memorization. Application Development questions reward identifying the dominant term in given pseudocode, not reciting textbook algorithms. Practice spotting O(n²) vs. O(n log n) at a glance.
• Practice with the on-screen calculator. You will not have access to MATLAB, Python, or a physical scientific calculator on exam day. Practice binary/hex conversions, modular arithmetic (for RSA problems), and reliability calculations with just the basic on-screen calculator.
• Use the 30-minute break strategically. The 8.5-hour appointment is a marathon. Eat a proper meal, hydrate, and walk around during the scheduled break. The second half of the exam requires fresh concentration — do not rush back to the computer.

Final Thoughts

The PE Computer Engineering exam has a small examinee population, so the published pass rate can swing from cycle to cycle. The difficulty lies not in any single topic being impossibly hard, but in the range of knowledge required — from bit-level data representation and digital logic through systems software, networks, and security concepts. Engineers who commit to a structured 16-week plan, work hundreds of practice problems across all 8 topic areas, and learn to navigate the reference handbook efficiently are well-positioned to pass on their first attempt.

At fetestprep.com, we offer PE Computer Engineering practice questions covering all 8 exam topics with detailed step-by-step explanations. Use them alongside your study plan to identify weak areas and build confidence before exam day.

Start early, study consistently, and trust the process. Your PE license is worth the effort.

Frequently Asked Questions

Disclaimer: This guide is an independent educational resource and is not affiliated with, endorsed by, or sponsored by NCEES. The “PE” exam and “NCEES” are trademarks of the National Council of Examiners for Engineering and Surveying. Exam specifications and content are subject to change; always refer to the official NCEES website for the most current information.